A Survey: Software-Managed On-Chip Memories

Year, pages: 2015, 1168 - 1200

Processors are unable to achieve significant gains in speed using the conventional methods. For example increasing the clock rate increases the average access time to on-chip caches which in turn lowers the average number of instructions per cycle of the processor. On-chip memory system will be the major bottleneck in future processors. Software-managed on-chip memories (SMCs) are on-chip caches where software can explicitly read and write some or all of the memory references within a block of caches. This paper footnoteThe work presented in this paper is an expansion of the authors' previously published work in the conference paper citeSMC-HPCS-10, and was carried out when the first author was a Ph.D. student in the Department of Computer Science at University of Victoria. analyzes the current trends for optimizing the use of these SMCs. We separate and compare these trends based on general classifications developed during our study. The paper not only serves as a collection of recent references, information and classifications for easy comparison and analysis but also as a motivation for improving the SMC management framework for embedded systems. It will also make a first step towards making them useful for general purpose multicore processors.

Alam, S., Horspool, N. 2015. A Survey: Software-Managed On-Chip Memories. In Computing and Informatics, vol. 34, no.5, pp. 1168-1200. 1335-9150.

Alam, S., Horspool, N. (2015). A Survey: Software-Managed On-Chip Memories. Computing and Informatics, 34(5), 1168-1200. 1335-9150.