Hardware Accelerator of Cartesian Genetic Programming with Multiple Fitness Units

In: Computing and Informatics, vol. 29, no. 6+

Z. Vašíček - L. Sekanina

Detaily:

Rok, strany: 2010, 1359 - 1371

Kľúčové slová:

Cartesian genetic programming, hardware accelerator, evolutionary circuit design, FPGA

O článku:

A new accelerator of Cartesian genetic programming is presented in this paper. The accelerator is completely implemented in a single FPGA. The proposed architecture contains multiple instances of virtual reconfigurable circuit to evaluate several candidate solutions in parallel. An advanced memory organization was developed to achieve the maximum throughput of processing. The search algorithm is implemented using the on-chip PowerPC processor. In the benchmark problem (image filter evolution) the proposed platform provides a significant speedup (170) in comparison with a highly optimized software implementation. Moreover, the accelerator is 8 times faster than previous FPGA accelerators of image filter evolution.

Ako citovať:

ISO 690:

Vašíček, Z., Sekanina, L. 2010. Hardware Accelerator of Cartesian Genetic Programming with Multiple Fitness Units. In Computing and Informatics, vol. 29, no.6+, pp. 1359-1371. 1335-9150.

APA:

Vašíček, Z., Sekanina, L. (2010). Hardware Accelerator of Cartesian Genetic Programming with Multiple Fitness Units. Computing and Informatics, 29(6+), 1359-1371. 1335-9150.