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Pipeline Implementation of Peer Group Filtering in FPGA

In: Computing and Informatics, vol. 31, no. 4
T. Kryjak - M. Gorgon

Details:

Year, pages: 2012, 727 - 741
Keywords:
Colour image processing, reconfigurable systems, FPGA, parallel algorithms
About article:
In the paper a parallel FPGA implementation of the Peer Group Filtering algorithm is described. Implementation details, results, performance of the design and FPGA logic resources are discussed. The PGF algorithm customized for FPGA is compared with the original one and Vector Median Filtering.
How to cite:
ISO 690:
Kryjak, T., Gorgon, M. 2012. Pipeline Implementation of Peer Group Filtering in FPGA. In Computing and Informatics, vol. 31, no.4, pp. 727-741. 1335-9150.

APA:
Kryjak, T., Gorgon, M. (2012). Pipeline Implementation of Peer Group Filtering in FPGA. Computing and Informatics, 31(4), 727-741. 1335-9150.