Dependability Evaluation of Time Triggered Architecture Using Simulation

Year, pages: 2004, 51 - 76

The method presented in this paper uses a generic C-language written simulation model of an embedded distributed computer system aimed for a safety-critical control application. The considered system is built using Time Triggered Architecture (TTA) concepts. The aim of the presented simulation method is to evaluate the system capability to tolerate a chosen category of faults. The model, being written in ANSI-C, is portable and machine-independent. Its structure is modular and flexible, so that the system to be studied and the experiment setting can easily be changed. The functionality of this model is demonstrated on a set of fault injection experiments aimed mainly to evaluate the correctness of the Time Triggered Protocol (TTP/C) that implements the abstract concepts of TTA. These experiments were done within the EU/IST project Fault Injection for Time triggered architecture (FIT).

Racek, S., Herout, P., Hlavička, J. 2004. Dependability Evaluation of Time Triggered Architecture Using Simulation. In Computing and Informatics, vol. 23, no.1, pp. 51-76. 1335-9150.

Racek, S., Herout, P., Hlavička, J. (2004). Dependability Evaluation of Time Triggered Architecture Using Simulation. Computing and Informatics, 23(1), 51-76. 1335-9150.