In: Computing and Informatics, vol. 35, no. 3
J. Quiros - S. Verlan - J. Viejo - A. Millan - M.j. Bellido
Details:
Year, pages: 2016, 687 - 718
Keywords:
Reconfigurable hardware, P systems, static P systems, FPGA, membrane computing, parallel implementations of membrane computing, simulator of membrane computing, hardware implementations of membrane computing, parallel implementations of static P systems,
About article:
In this article we present a simulator of non-deterministic static P systems using Field Programmable Gate Array (FPGA) technology. Its major feature is a high performance, achieving a constant processing time for each transition. Our approach is based on representing all possible applications as words of some regular context-free language. Then, using formal power series it is possible to obtain the number of possibilities and select one of them following a uniform distribution, in a fair and non-deterministic way. According to these ideas, we yield an implementation whose results show an important speed-up, with a strong independence from the size of the P system.
How to cite:
ISO 690:
Quiros, J., Verlan, S., Viejo, J., Millan, A., Bellido, M. 2016. Fast Hardware Implementations of Static P Systems. In Computing and Informatics, vol. 35, no.3, pp. 687-718. 1335-9150.
APA:
Quiros, J., Verlan, S., Viejo, J., Millan, A., Bellido, M. (2016). Fast Hardware Implementations of Static P Systems. Computing and Informatics, 35(3), 687-718. 1335-9150.