An Evolvable Combinational Unit for FPGAs

Year, pages: 2004, 461 - 486

A complete hardware implementation of an evolvable combinational unit for FPGAs is presented. The proposed combinational unit consisting of a virtual reconfigurable circuit and evolutionary algorithm was described in VHDL independently of a target platform, i.e. as a soft IP core, and realized in the COMBO6 card. In many cases the unit is able to evolve (i.e. to design) the required function automatically and autonomously, in a few seconds, only on the basis of interactions with an environment. A number of circuits were successfully evolved directly in the FPGA, in particular, 3-bit multipliers, adders, multiplexers and parity encoders. The evolvable unit was also tested in a simulated dynamic environment and used to design various circuits specified by randomly generated truth tables.

Sekanina, L., Friedl, Š. 2004. An Evolvable Combinational Unit for FPGAs. In Computing and Informatics, vol. 23, no.5-6, pp. 461-486. 1335-9150.

Sekanina, L., Friedl, Š. (2004). An Evolvable Combinational Unit for FPGAs. Computing and Informatics, 23(5-6), 461-486. 1335-9150.