Highly Efficient Twin Module Structure of 64-Bit Exponential Function Implemented on SGI RASC Platform

Year, pages: 2009, 127 - 137

This paper presents an implementation of the double precision exponential function. A novel table-based architecture, together with short Taylor expansion, provides a low latency (30 clock cycles) which is comparable to 32 bit implementations. A low area consumption of a single exp() module (roughtly 4% of XC4LX200) allows that several modules can be implemented in a single FPGAs.The employment of massive parallelism results in high performance of the module. Nevertheless, because of the external memory interface limitation, only a twin module structure is presented in this paper. This implementation aims primarily to meet quantum chemistry huge and strict requirements for precision and speed. Each module is capable of processing at speed of 200MHz with max. error of 1 ulp, RMSE equals 0.62

Wielgosz, M., Jamro, E., Wiatr, K. 2009. Highly Efficient Twin Module Structure of 64-Bit Exponential Function Implemented on SGI RASC Platform. In Computing and Informatics, vol. 28, no.1, pp. 127-137. 1335-9150.

Wielgosz, M., Jamro, E., Wiatr, K. (2009). Highly Efficient Twin Module Structure of 64-Bit Exponential Function Implemented on SGI RASC Platform. Computing and Informatics, 28(1), 127-137. 1335-9150.